Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a semiconductor device with buried gates (BG) and a method for fabricating the same.
As the size of semiconductor devices shrinks, compliance with diverse device characteristics and designing appropriate fabrication processes become more difficult. For example, in using 40 nm design rules, formation of structures of gates, bit lines, and contacts is reaching limits. Even if such small structures can be formed, desired device characteristics may not be obtained. To address such features, buried gate (BG) structures having gates buried in a substrate are used,
FIGS. 1A and 1B illustrate a conventional semiconductor device with buried gates. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view of the semiconductor device of FIG. 1A along line A-A′.
Referring to FIGS. 1A and 1B, a plurality of buried gates are formed over a substrate 11 having active regions 13 defined by an isolation layer 12, and landing plugs 14 are formed over the active regions 13 between the buried gates and the isolation layer 12. Each buried gate includes a trench 15 formed over the substrate 11, a gate insulation layer (not shown) on the surface of the trench 15, a gate electrode 16 filling a portion of the trench 15, and a gate sealing layer 17 filling the other portion of the trench 15. An inter-layer dielectric layer 18 is formed over the substrate 11 where the buried gates are formed. Storage node contact plugs 20 and bit lines 23 are formed over the inter-layer dielectric layer 18. Herein, a reference numeral ‘19’ denotes storage node contact holes, and a reference numeral ‘21’ denotes a damascene pattern. A reference numeral ‘22’ denotes bit line spacers, and a reference numeral ‘24’ denotes a bit line sealing layer.
According to the conventional technology, the storage node contact plugs 20 are formed after the bit lines 23 are formed. Here, using the conventional technology, the process margins of the process of forming the storage node contact plugs 20 may be decreased due to the presence of the bit lines 23. To address such a feature, a method of forming the storage node contact plugs 20 first and then forming the bit lines 23 was suggested. In such a method, a short may easily occur between the storage node contact plugs 20 and the land plugs 14 under the bit lines 23.
In addition, according to the conventional technology, the contact area between the landing plugs 14 and the storage node contact plugs 20 may be decreased since the storage node contact holes 19 are formed by etching the inter-layer dielectric layer 18 is etched at one step, for example, without consideration of the way that the formation of the storage node contact plugs 20 takes place, where the sidewalls of the storage node contact holes 19 are formed slanted due to etch characteristics.